1. Technical Field
The present invention relates to testing tools in general, and, in particular, to an apparatus for testing logic circuits. Still more particularly, the present invention relates to an apparatus for performing stuck fault testings within an integrated circuit.
2. Description of Related Art
Level-sensitive scan design (LSSD) tests are utilized to test the logic within integrated circuit devices in a reliable and efficient manner. During an LSSD testing, a chain of shift register latches (SRLs) is coupled to the inputs and outputs of an internal logic under test (LUT). Test data is scanned serially into one chain (i.e., the input chain) of the SRLs. When the input shift register is full, the data propagate through the LUT, and the data are then written into a second chain (i.e., the output chain) of the SRLs. The acquired data are then scanned serially out and compared to the expected data. If the acquired data do not match the expected data, the LSSD test will indicate that the LUT is not functioning properly. Such type of general functionality tests is commonly referred to as a stuck fault testing because it determines the existence of permanent (or stuck) errors in the LUT.
However, in addition to confirming the functionality of the LUT, it is also desirable to check the propagation delay through the LUT. That is, even when the stuck fault testing confirms that the LUT achieves the desired function, the corresponding circuit will not meet its performance specifications if it cannot produce the logic signals within an allocated time. The tests that determine propagation delays and detect propagation delay failures are commonly referred to as performance fault(or transition fault) testings.
The present disclosure provides an improved apparatus for performing stuck fault testings within integrated circuits.